Configuration register
| DIRINV | Direction invert. When 1, complements the DIR bit. |
| SIGMODE | Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal. |
| CAPMODE | Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. |
| INVINX | Invert Index. When 1, inverts the sense of the index input. |
| CRESPI | Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| INXGATE | Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |